1. Field of the Invention
The present invention generally relates to an operation method for a non-volatile memory. More particularly, the present invention relates to an operation method for a non-volatile memory under low voltage.
2. Description of Related Art
The erasable and programmable read only memory (EPROM) and the electrically erasable programmable read only memory (E2PROM) are classified to be the non-volatile memory during the application of the integrated circuit. Where the electrical erasable and programmable read only memory contains the advantages includes writable, erasable, retaining the data even after the electricity is terminated, therefore, it is well accepted memory device to be applied for personal computers and electrical equipments.
According to the current development of the non-volatile memory devices, the one with electrical trapping structure can be, for example, Silicon-Oxide-Nitride-Oxide-Silicon (SONOS), Metal-Oxide-Nitride-Oxide-Silicon (MONOS) . . . etc, the electron trapping layer where the electron can fill in restricted area and less defected sensitivity to the tunneling oxide layer, therefore less possibility for current leakage and one memory cell can save 2 bit, therefore better efficiency for the device can be expected.
In general, the operation method for the above mentioned read only memory which contains the electron trapped layer is, for example, programming by the channel hot electron injection (CHEI) and erasing the data through the band to band induced hot hole injection, or by Flower-Nordheim tunneling (FN Tunneling) to fill electron into the electron trapping layer for erasing and programming by band to band induced hot electron injection.
According to the above mentioned operation method, 10 volts are required for the controlling gate to perform the programming by channel hot electron injection; and 20 volts are required for the controlling gate if performing the erasing through FN tunneling; therefore the tolerance for the high voltage is required for the electron trapping layer of the read only memory. However, if the electron trapping layer of the read only memory is requested to be with high voltage tolerance, considering the fabrication for the integration of the peripheral electrical circuit, the fabrication of the memory device, will be more complicated, therefore, the cost will be increased.